CISC Vs RISC Achitectures

CISC Vs RISC

          The performance of a CPU is highly dependent on its internal architecture. Mainly there are two architectures. They are,

CISC Architecture

        

          CISC stands for Complex Instruction Set Computing. Traditional theory states that CPUs can be made quicker by adding more and more complexity into the instructions of the instruction set. This architecture can execute several low level operations such as load from memory, an arithmetic operations and a memory store all in a single instruction.
         CISC is the more advanced architecture compare with RISC architecture. It can multiply two logical numbers in one step. In CISC Architecture no of bits per instruction is high. That means it can have high capacity. CISC is used in computer Micro processors & the devices which have high speed processing power.

RISC Architecture

              RISC stands for Reduced Instruction Set Computing. It states that the best performance can be achieved by reducing the time taken to execute any given instruction. Rather than have complex instructions that require many clock cycles (more on this later) to complete, RISC chips use very simple instructions that could be performed in fewer clock cycles. Performance can then be improved by making the cycles shorter.

             Compare to CISC, RISC haven’t that much of process power. It can’t multiply two logical numbers in one step. It uses add and shift function to do that.

Multiply function

CISC Architecture-    00010110 + 00000110 = 1000100     ; It can multiply it one step.

RISC Architecture-   00010110 + 00000110 =?  But here we can’t do it in one step because it doesn’t have a multiplying function.

Therefore it uses add & shift

Von Numann & Harvard Memory Architecture

Von Neumann

           

                In the von Neumann architecture CPU can either read an instruction or read/write data from/to the memory. Both of these operations cannot occur simultaneously as the data and instructions use the same system bus. This means that it is necessary to fetch instruction and data from the same memory space, which limits bandwidth because it can only transmit one piece of data or one instruction at a time.

 Harvard Architecture

The most obvious characteristic of the Harvard Architecture is that it has two different data buses to. The contacts are CPU to RAM and CPU to ROM.  Using these buses it is possible to access program memory and data memory simultaneously. Typically, code (or program) memory is read-only and data memory is read-write. A Harvard architecture microcontroller can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway. Compare to von numann architecture Harvard Architecture can achieve higher clock speeds; caches are useful as the memory speed is proportionally slower. Harvard architectures tend to be targeted at higher performance systems, and so caches are nearly always used in such systems. Harvard Micro processors can be much faster than a von Neumann Micro processor because data and program do not contend for the same information pathway, and storing the program in an immutable read-only memory can result in vast reliability improvements.

           Thank you everybody, if you are struggling with any of this information, please post a comment. Comments are welcome.